1. Field of the Invention
This invention relates to semiconductor memory design and particularly to skip-over redundancy repair operations.
2. Description of Background
Skip-over redundancy is a method used in semiconductor memory design at IBM to replace certain defective memory elements and associated circuitry with non-defective spare elements and associated circuitry. The method involves several stages of chip testing. One of the early stages of chip test includes a “scan” test which tests some of the basic test infrastructure built into the chip. If a chip does not pass this basic test, it is considered a non-repairable defective chip. If the chip passes the scan test testing will continue. Later in the test sequence, the memory elements and associated circuitry are tested. If a defective element is found and it is determined that the element can be repaired with a spare element via the skip-over redundancy scheme, the repair will be made and the memory retested.
Scan operations are an integral part of both chip testing and redundancy repair actions. These operations are used to read the current state of chip latches and to load information into chip latches. Some of the latches that can be loaded hold the information needed to repair defective memory elements and associated circuitry. Certain manufacturing defects in memory elements can cause the chip to fail basic scan operations. Some of these defects can be in elements and/or circuitry that are repairable using redundancy; however since the chip cannot complete scan operations the chip never reaches that part particular step in the test/repair sequence. These defects may therefore be repairable defects, that once repaired, would also permit the scan operation to continue, but since they cause the chip to fail the “scan” operation, they are never tested or repaired, resulting in a loss of chip yield